Reading or accessing of bit cells in read only memories (ROM) may result in cross talk due to surrounding bit-lines that may be discharged during the read operation. In sub-micron semiconductor technologies, large capacity and dense ROM arrays, bit-lines may have large capacitances. Distances between the bit-lines may be greatly reduced due to the density of the arrays. In these conditions, cross talk issues may occur. The cross talk may result in a zero being read instead of a one due to undesired discharge of the accessed bit-line.
As an example of such cross talk, consider a bit-cell set to one with a neighboring bit cell set to zero. A parasitic coupling capacitance exists between the two bit-lines. During the precharge of the bit-lines, just prior to reading the bit-cell, the bit-lines are set to one, corresponding to Vdd. During the reading, a word line rises to one. Then the bit-line to be read is supposed to stay at the precharge level of one since the bit-cell is one. The neighboring bit-line is discharged, since it has no charge, corresponding to a zero.
Due to cross talk, however, the bit-line to be read is partially discharged through the neighboring bit-line. This unwanted bit-line discharge, if large enough, may cause a sense amplifier to switch, such that a zero is read from the bit-line to be read instead of the one stored in the corresponding bit cell. This may occur even if the discharge of the bit-line to be read is not complete. If there are two neighbor bit-lines, both at zero, the discharge of the bit-line to be read may occur via parasitic capacitance coupling of both neighbor bit-lines.
In some ROM devices, the precharge stays active during reading through pull-up transistors that are always on. This avoids cross talk, since the bit-line to be read is driven to Vdd during the reading. However, it results in additional power consumption that is not suitable for lower power applications. Static bit-line shields may be created by inserting vertical metal lines between adjacent columns to decrease parasitic capacitance by increasing distance between adjacent bit-lines. This approach consumes chip area and decreases the overall storage density achievable.
Some ROM devices implemented a dynamic bit-line shield such that during reading, all the unread bit-lines stay precharged to Vdd. Static current is important with such an architecture since bit-lines that are not read, stay driven to Vdd. Some low power ROMs may utilize high capacitive CMOS circuits to avoid cross talk. All the bit lines are discharged to zero before charge sharing. Such CMOS circuits decrease potential storage density, as a two extra bit lines are used for every 16 bit lines. Complex sensing circuitry may also be needed for such ROM. Half-swing circuitry is also not adapted for low voltage circuits.
In still further ROM, a content aware design framework may be used to reduce cross talk. The number of cells programmed to zero or one in each column may be modified to change the value of capacitance between two bit-lines. Such frameworks increase the complexity of reading circuitry, increase the area of the memory due to additional rows, and may not be totally efficient depending on ROM code.
In US Patent Application Publication No: 2006-0171240 to M. Combe, bit-lines of a memory device are arranged by an interleaving of even and odd bit-lines, and are segregated into an even and an odd bank. A discharge network discharges the banks alternately to reduce cross talk. One bank may be discharged just prior to selection of the other bank for reading. A discharge delay may be used to ensure that sense amplifiers do not detect signals during the discharge.